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这篇文章做的是2.4GHz频段的Type I PLL,利用gain-boosted saturated PFD扩展了PLL的锁定范围,同时利用S&H电路的synchronous peak tracking loop filter降低了I类PLL的参考杂散。
提出的PLL框架如下:如下图所示,传统PFD会存在一个cycle slipping的问题。
Conventional 3-state PFDs suffer from cycle-slipping, attributed to the reset of the PFD output signal when the input phase difference is 2n, where n = ±1, 2, 3 . . . , as shown in Fig. 4(a). The main concern with cycle slipping in a conventional Type-II loop is the reduced frequency acquisition speed. On the other hand, cycle slipping can also limit the frequency lock range in Type-I loops.
(b)和©的增益曲线都能克服这个问题。
文章提出的SPFD结构如下: 多加一级触发器可以在 Δ ϕ \Delta \phi Δϕ超过 2 π 2\pi 2π的时候钳住reset电平,保持恒定值不变。常见的I类PLL结构有这些:
值得一提的是(a)中的在前向路径中加一个Linear Amplifier来提高前向增益,从而提高PLL的锁定范围。 都是基于I类PLL这个公式作出的改变:A. Sharkia, S. Aniruddhan, S. Mirabbasi and S. Shekhar, “A Compact, Voltage-Mode Type-I PLL With Gain-Boosted Saturated PFD and Synchronous Peak Tracking Loop Filter,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 1, pp. 43-53, Jan. 2019, doi: 10.1109/TCSI.2018.2858197.
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